Document Type and Number:
Japanese Patent JPS5427681
Kind Code:
B1
Abstract:
1,066,925. Automatic exchange-systems. AUTOMATIC ELECTRIC LABORATORIES Inc. Oct. 14, 1963 [Oct. 16, 1962; March 27, 1963; April 12, 1963; Sept. 16, 1963], No. 44119/66. Divided out of 1,066,921. Heading H4K. A translator for use in the exchange system of the parent Specification comprises: an access shift register into which data from a register sender is inserted; a magnetic drum which stores, inter alia, routing and equipment number digital data; a cyclically operable address generator that produces, in turn, the various directory numbers of the exchange; and a comparator which under the influence of some of the digits in the shift register compares the other digits in the shift register with either the output of the drum or the generator (which actually forms part of the drum) an 1 when coincidence occurs causes the data in the shift register to be replaced by the data then appearing in the generator or drum respectively. The details of the exchange are described in the parent Specification and for a full understanding of the following, (including the conventions used therein) reference to the parent Specification will be necessary. The translators perform the following functions: (a) Translation of a called party's directory number into an equipment number. (b) Translation of a calling party's equipment number into a directory number. (c) Provision of routing instructions; and (d) Provision of special service instructions for such purposes as repertory dialling and automatic call transfer. Data is inserted on the drums from a control console typewriter. The associated logic utilizes standard packages consisting of transistor/component arrays mounted on printed circuit cards. Translators are provided on a basis of one per 20 R.S. groups. The latter are cyclically scanned at the translator end of the links therebetween and a request from one of them causes scanning to stop and'a GO signal to be reverted. Data is transmitted in serial form to a translator receiver which decodes the data and passes it in parallel form to the process circuitry of the translator. After translation the data is re-encoded in serial form and sent to the register which requested service. The scanner is restarted. Translator, particular description.-A register group identifier comprises an allotter consisting of a 21 position flip-flop chain SC (F11) which has a 32À5 Ásecs. cycle time. A request signal from an R.S. group in conjunction with the appropriate pulse output of the allotter opens gates AP, LG, so as to set FFLO, to connect the RS to the translator transceiver and to stop the allotter. FFID (F27) in the translator control circuit sets in response to FFLO. It is ensured that the latter only sets in the middle of a time slot, so that the necessary 1À6 Ásec. for FFID to respond and hence stop the allotter is allowed and spurious request signals are prevented from seizing the translator. The AP gates also control the particular translator to be allotted to the calling R.S. group. After 4 Ásecs. the translator returns a GO signal via gates B1-B20 to the calling R.S. which thereupon transmits serial data to the translator transceiver (F12) which is synchronized with the register transceiver. The 64 incoming data bits preceded by two " 0 " bits and a prefix bit are shifted through a flip-flop shift register AA until the prefix bit sets FFPF(F13) which indicates to translator control that the data is all stored in the access register AA. Even parity is checked by a flip-flop BP. The two " 0 " bits are stored in flop-flops BF1 and 2. In the translator control, FFRE(F23) is set by FFID so that in response to FFPF flip-flops RC, PR1, PR2 and PR3 also become set to cause processing of the data in AA. On completion of the translation, the required data is stored in the transceiver shift register, FFSE is set and the lead DCS provides zero inputs which cause the data to be serially shifted out of the transceiver and transmitted to the R.S. When the shift register is empty FFES(F90) sets so as to send an " end of send " signal to the R.S. and to switch the translator transceiver to its idle state. In addition FFID is normally reset at this time to clear the translator control. However, if a fault occurs FFRT is set instead to cause the alternative translator to be utilized for all calls (from the 40 R.S. groups served by these two translators) until the fault is cleared. The translation data, which is obtained from a magnetic drum or from logic circuitry, comprises up to 9 routing digits, up to 3 sender instruction digits (for controlling the sender mode) and up to 4 processing digits. The latter are returned to the translator on subsequent access by the R.S. so that they can control the particular, type of processing required by this access. They include information as to how many digits a subscriber is expected to dial and how many should be transferred to the translator during subsequent access and also the address of the magnetic drum (if there is more than one) to be used. A logic circuit translation occurs immediately if incomplete or incorrect incoming data is received or if a call is to be barred. In dependence on the informaion available e.g. directory number, equipment number or code number, the translator control accesses the segments of the drum in a different order and then sequentially scans for the relevant address. The translation in respect of this address is stored in a buffer MR. A coincidence buffer CN compares the input data in AA with the drum output data in order to determine the relevant information for return to the register sender.
Application Number:
JP3573266A
Publication Date:
September 11, 1979
Filing Date:
June 04, 1966
Export Citation:
International Classes:
H04Q3/52; H04Q3/545; H04Q3/78; (IPC1-7): H04Q3/42; H04Q3/52