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Patent Searching and Data


Title:
AD CONVERSION METHOD
Document Type and Number:
Japanese Patent JPS5458341
Kind Code:
A
Abstract:

PURPOSE: To make accurate the A/D converter of poor accuracy and to enable to made easy circuit integration, by adding the digital memory memorizing correct value to the circuit.

CONSTITUTION: The output of high accuracy 4 can be obtained by memorizing 2 the correct value from the reference A/D converter 5 to all the outputs of the A/D converter 1 of poor accuracy and by separating the converter 5 after the completion of memory. Further, if the accuracy of upper rank 4-bit is poor and the error is corrected at the 4-bit of lower rank, the difference between the output of the A/D converter 11 of poor accuracy and the output of the refernce A/D converter 51 is obtained at the subtractor 71. Next, the signals 3-1 to 3-4 of the higher rank 4-bit are written in the memory address 21 for the address. Similarly, the input voltage is sequentially changed and the error in the upper rank 4-bit of the converter 11 is all memorized 21. Next, the memory 21 is read out and it is converted into readout mode, allowing to each corrective output according to the outputs 3-1 to 3-4. This is added 72 to the outputs 3-1 to 3-4 and accurate output 8 can obtained


Inventors:
MAIO KENJI
HOTSUTA MASAO
YOKOZAWA NORIO
Application Number:
JP12451477A
Publication Date:
May 11, 1979
Filing Date:
October 19, 1977
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03M1/10; H03M1/16; H03M1/38; H03M13/00; (IPC1-7): H03K13/02
Domestic Patent References:
JPS51128254A1976-11-09
JPS5242058A1977-04-01
JPS4821414A