Title:
ADDER CIRCUIT
Document Type and Number:
Japanese Patent JP3260197
Kind Code:
B2
Abstract:
PURPOSE: To add signed analog data by connecting inverters including feedback lines in series in many stages to secure the output precision and selectively inputting data to one inverter in accordance with the sign of data.
CONSTITUTION: An adder circuit is provided with two stages of inverters INV1 and INV2 connected in series, and outputs of inverters INV1 and INV2 are fed back to respective inputs through capacitors C21 and C23. These inverters have the output precision and the linearity secured by the constitution including sufficient high gains and feedback lines. Capacitive couplings CP1 and CP2 where plural capacitors are connected in parallel are connected to inputs of inverters INV1 and INV2, and corresponding capacitors of these capacitive couplings are connected to outputs of common switching means SW1, SW2.... These switching means are switched by a sign signal S indicating the polarity of an input voltage D, and data is selectively inputted to one inverter in accordance with the sign of data.
Inventors:
Kotobuki Guoliang
Yang Yasuyasu
Nao Takatori
Makoto Yamamoto
Yang Yasuyasu
Nao Takatori
Makoto Yamamoto
Application Number:
JP5150293A
Publication Date:
February 25, 2002
Filing Date:
February 16, 1993
Export Citation:
Assignee:
Takayama Co., Ltd.
Sharp Corporation
Sharp Corporation
International Classes:
G06G7/14; (IPC1-7): G06G7/14
Domestic Patent References:
| JP58127271A | ||||
| JP1258188A | ||||
| JP5988756U |
Other References:
【文献】永田譲「IC演算増幅器とその応用」日刊工業新聞社,(S53.1.30)p.11~17
Attorney, Agent or Firm:
Makoto Yamamoto
Previous Patent: INCOMBUSTIBLE PAPER AND ITS PRODUCTION
Next Patent: CONNECTION PATH INFORMATION RESTORATION SYSTEM
Next Patent: CONNECTION PATH INFORMATION RESTORATION SYSTEM