To enable miniaturization and power consumption reduction by making code expansion to input data unnecessary when adding the input data described with the complement of N.

A first adder is composed of adders 25 and 26 for inputting most significant elements by digits and adders 21-24 for inputting the other element by digits. A multiplier 31 multiplies '-8' to the output of the adder 25 and a multiplier 32 multiplies '-16' to the output of the adder 26. A second adder 33 adds the outputs of individual multipliers 27-32. Thus, it is not necessary to align the number of elements of the input data with the number of elements of output data and a positive/negative integer described with the complement of '2' can be inputted without expanding the code. As a result, in comparison with a conventional adder, which requires code expansion to the input data, the number of first adders is reduced and the configuration thereof can be simplified as well.