Title:
ANALOG ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP2004157757
Kind Code:
A
Abstract:
To improve the performance of an analog arithmetic circuit, and to reduce the area of the circuit.
Multiplying circuits 1a to 1c multiply the product of each output value of a neuron at a preceding stage and synapse load values stored in each of synapse load storing means 5a to 5c, and the sum of the products is stored into a product sum arithmetic result storing means 2. A non-linear arithmetic storing means 4 applies a non-linear transformation operation to the product sum arithmetic results based on the non-linear physical characteristics of the non-linear arithmetic storing means 4, and stores the results.
Inventors:
MORI KATSUHIKO
MATSUGI MASAKAZU
MITARAI HIROSUKE
MATSUGI MASAKAZU
MITARAI HIROSUKE
Application Number:
JP2002322719A
Publication Date:
June 03, 2004
Filing Date:
November 06, 2002
Export Citation:
Assignee:
CANON KK
International Classes:
G06G7/60; G06G7/16; G06N3/063; (IPC1-7): G06G7/60; G06G7/16; G06N3/063
Attorney, Agent or Firm:
Keizo Nishiyama
Yuichi Uchio
Yuichi Uchio