Title:
アナログ演算回路
Document Type and Number:
Japanese Patent JP6678797
Kind Code:
B2
Abstract:
The power consumption of an analog arithmetic circuit is reduced. The analog arithmetic circuit includes a plurality of first circuits. An output terminal of the k-th (k is a natural number) first circuit is connected to an input terminal of the k+1-th first circuit. Each of the first circuits includes a memory circuit which holds an analog signal, a second circuit which performs arithmetic processing using the analog signal, a switch which controls power supply to the second circuit, and a controller. The conduction state of the switch included in the k-th first circuit is controlled by the controller included in the k+1-th first circuit. The arithmetic processing performed by the second circuit included in the k+1-th first circuit is started by the controller included in the k+1-th first circuit.
Inventors:
Yoshimoto Kurokawa
Takayuki Ikeda
Shunpei Yamazaki
Takayuki Ikeda
Shunpei Yamazaki
Application Number:
JP2019087336A
Publication Date:
April 08, 2020
Filing Date:
May 07, 2019
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G06G7/12; H01L21/8234; H01L27/06; H01L27/088; H01L29/786
Domestic Patent References:
| JP2004343163A | ||||
| JP2007336377A | ||||
| JP2013211840A |
Foreign References:
| US20070290914 |