アナログ電子ニューラルネットワーク

Japanese Patent JP6647429

B2

The present invention concerns a method of programming an analogue electronic neural network (1) comprising a plurality of layers of somas (3). Any two consecutive layers of somas (3) are connected by a matrix of synapses (5). The method comprises: applying (a) test signals to inputs of the neural network (1); measuring (b) at a plurality of measurement locations in the neural network (1) responses of at least some somas (3) and synapses (5) to the test signals; extracting (b) from the neural network (1), based on the responses, a first parameter set characterising the behaviour of the at least some somas (3); carrying out (c) a training of the neural network (1) by applying to a training algorithm the first parameter set and training data for obtaining a second parameter set; and programming (d) the neural network (1) by using the second parameter set. The invention also relates to the neural network (1) and to a method of operating it.

WO/2020/221797	COMPUTATIONALLY EFFICIENT IMPLEMENTATION OF ANALOG NEURON
JPH0591901	COVERING ELEMENT ADAPTABLE PARTICULARLY FOR SOCCER SHOES
WO/2023/123648	CONVOLUTIONAL NEURAL NETWORK ACCELERATION METHOD AND SYSTEM BASED ON CORTEX-M PROCESSOR, AND MEDIUM

Jonathan Jacob Moses Bynas
Daniel Lawrence Nail

JP2018562704A

February 14, 2020

February 17, 2017

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UNIVERSITAT ZURICH

G06N3/063; G06G7/60; G06N3/08

WO2013108299A1

OGRENCI, Arif Selcuk et al.,FAULT-TOLERANT TRAINING OF NEURAL NETWORKS IN THE PRESENCE OF MOS TRANSISTOR MISMATCHES,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING,2001年 3月,VOL.48, NO.3,p.272-281,URL,https://ieeexplore.ieee.org/document/924069
LIU, Beiye et al.,Vortex: Variation-aware Training for Memristor X-bar,2015年 7月27日,p.1-6,URL,https://ieeexplore.ieee.org/stamp.jsp?tp=&arnumber=7167198

Kato Takushi
Okuzumi Shinobu

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