Title:
ANALOG MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JP3050185
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an analog multiplication circuit for a high frequency with less carrier signal leakage.
SOLUTION: For this analog multiplication circuit, a gilbert cell type multiplication circuit is constituted of a first differential circuit by a pair of transistors 605 and 606, a second differential circuit by a pair of transistors 601 and 602 and a third differential circuit by a pair of transistors 603 and 604. Then, to a load resistor 627 of the transistor 601 and a load resistor 628 of the transistor 604, carrier signal overshoot compensation means 101 and 102 are respectively connected in parallel. Since the carrier signal overshoot compensation means 101 and 102 are operated so as to reduce an overshoot current generated, when the transistors 601 and 603 and the transistors 602 and 604 are turned on, flowing to the respective load resistors 627 and 628, the overshoot of carrier signals is reduced, and the leakage to an output terminal of the carrier signals is reduced.
Inventors:
Masaho Mineo
Application Number:
JP28041997A
Publication Date:
June 12, 2000
Filing Date:
October 14, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06G7/163; H03C1/54; H03D7/14; (IPC1-7): H03D7/14; G06G7/163; H03C1/54
Domestic Patent References:
| JP8316737A | ||||
| JP5312323B2 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)