Title:
ANALOG MULTIPLIER
Document Type and Number:
Japanese Patent JP2004110530
Kind Code:
A
Abstract:
To provide a highly accurate analog multiplier constituted by using inexpensive general-purpose parts.
The analog multiplier for calculating the product of two analog signal input values and outputting the calculation result as an analog signal value comprises: a pulse width modulation circuit 1 for applying pulse width modulation to one signal input; an analog switch circuit 2 which is controlled by the output of the pulse width modulation circuit 1 and turns on and off the other signal inputs intermittently; and a low-pass filter circuit 3 passing only the low-frequency component of the output of the analog switch circuit 2. The output of the low-pass filter circuit 3 is outputted as the result of multiplication operation.
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Inventors:
YAMADA YASUJI
KATO HISASHI
KATO HISASHI
Application Number:
JP2002273491A
Publication Date:
April 08, 2004
Filing Date:
September 19, 2002
Export Citation:
Assignee:
CHUO SEISAKUSHO
International Classes:
G06G7/161; (IPC1-7): G06G7/161
Attorney, Agent or Firm:
Tatsuo Watanuki
Akio Najima
Fumio Yamamoto
Akio Najima
Fumio Yamamoto