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Patent Searching and Data


Title:
ANALOG MULTIPLYING CIRCUIT
Document Type and Number:
Japanese Patent JP2740440
Kind Code:
B2
Abstract:

PURPOSE: To enable high-linearity operation even under a low power supply voltage by providing first and second reference current generating circuits for controlling first and second differential amplifying circuits to which a first operation input signal to be a multiplying signal is impressed corresponding to the output of a third differential amplifying circuit.
CONSTITUTION: This circuit is provided with a first differential amplifying circuit I composed of a first differential pair Q1-Q2 and a first variable current source 101 so as to fetch a first differential input signal, second differential amplifying circuit II composed of a second differential pair Q3-Q4 and a second variable current source 102 so as to fetch the first differential input signal, and third differential amplifying circuit III equipped with first and second output terminals with mutually opposite phases so as to fetch a second differential input signal. Then, a reference current generating circuit IV is provided between the first output terminal and the first variable current source 101, and a second reference current generating circuit V is provided between the second output terminal and the second variable current source 102. Thus, the number of steps to longitudinally pile up transistors can be decreased to two steps while keeping a constant current operation.


Inventors:
Tsuneo Tsukahara
Ishikawa Masayuki
Application Number:
JP2079993A
Publication Date:
April 15, 1998
Filing Date:
January 14, 1993
Export Citation:
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Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Domestic Patent References:
JP333989A
Attorney, Agent or Firm:
Masataka Kobayashi