Title:
ARITHMETIC PROCESSOR
Document Type and Number:
Japanese Patent JP2729121
Kind Code:
B2
Abstract:
PURPOSE: To selectively restart only a device in which a microprocessor is disabled to operate.
CONSTITUTION: At the time of detecting the operation disablement of the microprocessor 2, a microprocessor down detecting circuit 4 sends an inter-device intra-interface reset signal 111 in an inter-device interface 100 to an OR circuit 8 as a reset command signal 112. The OR circuit 8 sends the signal 112 inputted from the circuit 4 to the microprocessor 2, an interface controller 3 and arithmetic processing circuits 6, 7 as an intra-device reset signal 113 to respectively start the microprocessor 2, the interface 3 and the circuits 6, 7.
Inventors:
HIUGA NORIO
Application Number:
JP33245591A
Publication Date:
March 18, 1998
Filing Date:
November 21, 1991
Export Citation:
Assignee:
KOFU NIPPON DENKI KK
International Classes:
G06F1/24; G06F11/14; G06F11/28; G06F15/78; (IPC1-7): G06F1/24; G06F11/14; G06F11/28; G06F15/78
Domestic Patent References:
| JP3126118A | ||||
| JP1191916A | ||||
| JP6184902U | ||||
| JP2925231U |
Attorney, Agent or Firm:
Yanagi Kawa Shin
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