Title:
ARITHMETIC UNIT AND PRODUCT SUM OPERATION SYSTEM
Document Type and Number:
Japanese Patent JP2021002133
Kind Code:
A
Abstract:
To improve the accuracy of operation in an analog circuit performing product sum operation.SOLUTION: An arithmetic unit has first and second arithmetic circuit parts. Product sum signals output from a plurality of output lines of the first arithmetic circuit part or signals generated on the basis of the product sum signals are inputted to a plurality of input lines of the second arithmetic circuit part. An extending direction of the plurality of input lines of the first arithmetic circuit part and an extending direction of the plurality of output lines of the second arithmetic circuit part are parallel with each other. When ends nearer to the second arithmetic circuit part, of two endmost output lines of the first arithmetic circuit part are defined as first and second ends respectively and ends nearer to the first arithmetic circuit part, of two endmost input lines of the second arithmetic circuit part are defined as third and fourth ends respectively, a position in a first direction of at least one of the first and second ends is a position between a position of the third end and a position of the fourth end or a position in the first direction of at least one of the third and fourth ends is a position between a position of the first end and a position of the second end.SELECTED DRAWING: Figure 29
Inventors:
FUJINAMI YASUSHI
Application Number:
JP2019114592A
Publication Date:
January 07, 2021
Filing Date:
June 20, 2019
Export Citation:
Assignee:
SONY CORP
International Classes:
G06G7/60; G06G7/14; G06G7/16; G06N3/063
Attorney, Agent or Firm:
Junichi Omori
Mitsuru Takahashi
Teppei Nakamura
Ori Akira
Masayoshi Sekine
Ayako Kaneko
Shintaro Kanayama
Chiba Ayako
Shiraka Tomohisa
Mitsuru Takahashi
Teppei Nakamura
Ori Akira
Masayoshi Sekine
Ayako Kaneko
Shintaro Kanayama
Chiba Ayako
Shiraka Tomohisa