Title:
AUTO-OFFSET CANCEL CIRCUIT
Document Type and Number:
Japanese Patent JP3463316
Kind Code:
B2
Abstract:
PURPOSE: To reduce a circuit cost by excluding the outside of a capacitor, and decreasing a chip area.
CONSTITUTION: This circuit is constituted of MOS switches 101-106 and a capacitor 112 connected with an operating amplifier 107. At the time of sampling the input offset voltage of the operating amplifier 107 in the capacitor 112, a charge is stored in the capacitor 112 by considering a parasitic capacitor 113 of the MOS switches 101-106. That is, at the time of an offset cancel mode, the charge is stored in the capacitor 112 by expecting the effect of the parasitic capacitor 113 in an operating amplifier operating mode.
Inventors:
Toshiro Karaki
Application Number:
JP14320493A
Publication Date:
November 05, 2003
Filing Date:
June 15, 1993
Export Citation:
Assignee:
Nissan Motor Co., Ltd
International Classes:
G06G7/12; (IPC1-7): G06G7/12
Domestic Patent References:
| JP5647766A | ||||
| JP5711812U |
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