Title:
AVERAGING CIRCUIT
Document Type and Number:
Japanese Patent JP3042567
Kind Code:
B2
Abstract:
PURPOSE: To provide a small-sized high-speed averaging circuit by connecting the voltage follower output of CMOS to common output.
CONSTITUTION: By connecting the parallelly-connected same plural depression type CMOS T1, T2 and T3 to the common output DO in the voltage follower output D1, D2 and D3 and applying input voltages (x), (y) and (z) to the gates of the respective CMOS, the average value of the input of the respective CMOS is generated at the common output DO.
Inventors:
Kotobuki Guoliang
Yang Yasuyasu
Wiwat Wonwalla Wipat
Nao Takatori
Makoto Yamamoto
Yang Yasuyasu
Wiwat Wonwalla Wipat
Nao Takatori
Makoto Yamamoto
Application Number:
JP24869092A
Publication Date:
May 15, 2000
Filing Date:
August 25, 1992
Export Citation:
Assignee:
Takatori Ikueikai Co., Ltd.
Sharp Corporation
Sharp Corporation
International Classes:
G01R19/00; G06G7/14; G06G7/12; H03F3/30; (IPC1-7): G06G7/12; H03F3/30
Domestic Patent References:
| JP58223875A |
Other References:
【文献】鈴木八十二著、「電子科学シリーズ(71)、CMOSの応用技法」、産報出版発行、1978年8月20日、P12-P29
Attorney, Agent or Firm:
Makoto Yamamoto