PURPOSE: To reduce a parasitic transistor by a method wherein two P-type diffusion regions for isolation use are formed by sandwiching an N-type dummy region as in usual cases, a width of the P-type buried diffusion regions connected to lower parts of the P-type isolation regions is made large and the regions are approached to N-type buried diffusion regions surrounding them.

CONSTITUTION: N-type buried regions 3, 3' are diffused and formed in peripheral parts of a P-type substrate 1; an N-type layer is grown epitaxially on the whole surface including them. Then, an N-type dummy region 6 is partitioned in the central part of the layer 2; P-type isolation regions 5 are diffused along both sides of the region; P-type buried regions 4 are formed at their lower parts; a bipolar IC is formed; during this process, a parasitic NPN transistor which uses the regions 2 and 3 as emitters, the regions 4 and 5 as bases and the regions 2' and 3' as collectors is generated. Accordingly, a width of the regions 4 is made large and these regions are approached to the regions 3, 3'; a direct- current current amplification factor of the parasitic transistor is reduced; a parasitic operation is made smaller without increasing a chip area.