Title:
DYNAMIC-RANDOM-ACCESS-MEMORY AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH02156665
Kind Code:
A
Abstract:
PURPOSE: To provide a DRAM memory array of super high density by, when manufacturing an IC array containing plural memory cells arrayed vertically, configuring it with plural DRAMs with FETs arrayed vertically. CONSTITUTION: A memory array 1 configured with plural DRAM cells 2 with FETs arrayed vertically, with each cell 2 provided with an N-type source area 3, a P-type channel area 4, and an N-type extension drain area 5, and a gate electrode 6 is attached with a polycrystal Si where a related area 4 is separated and insulated with a gate oxide film 7. The area 5 is also separated and insulated from an N<+> -type Si substrate 8 with an oxide layer 9, with an N<+> polycrystal area 11 directly connected to the substrate 8. The cells 2 are separated with a composite nitride film/oxide insulation element 13, with a thermal insulation oxide area 10 and the area 11 separated with the element 13 as well. A polycrystal Si area 12 capped with a thermal oxide layer 14, the part between gates 6 and the area above it are filled with a chemical vapor-deposited oxide area 15 whose upper surface is flat, with a conductive bit line 16 orthogonal to the gate 6 provided on it.
Inventors:
DEIIJIE SHIIIN
SANGU HO DOONGU
SANGU HO DOONGU
Application Number:
JP26313789A
Publication Date:
June 15, 1990
Filing Date:
October 11, 1989
Export Citation:
Assignee:
IBM
International Classes:
H01L27/10; H01L21/3065; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108
Domestic Patent References:
| JPS62268158A | 1987-11-20 | |||
| JPS6329571A | 1988-02-08 |
Attorney, Agent or Firm:
Tokuda Nobuya (2 outside)