To provide a both edge differentiation circuit that has no restriction for a time of a high period and a low period of an input signal and obtain a stable output.

The both edge differentiation circuit is provided with an inverter 5, NAND gates 1, 4, NAND gates 2, 3 configuring an RS latch circuit, and CR delay circuits 6, 66. An input terminal to which an input signal is applied is connected to the NAND gate 1 and an input terminal of an inverter 5, an output terminal of the inverter 5 is connected to the input terminal of the NAND gate 4, output terminals of the NAND gates 1, 4 are connected to the input terminal of the RS latch circuit and also connected to differentiation signal output terminals 20, 30, and the output terminals of the NAND gates 2, 3 of the RS latch circuit are connected to the other input terminals of the NAND gates 1, 4 via the CR delay circuits 6, 66 in crossing with each other.