PURPOSE: To apply a sequence to plural direct memory access transfers, interruption requests and the like and to adjust a transfer speed between buses by providing an empty area managing circuit, an interruption request circuit and a load control circuit in a buffer control device.

CONSTITUTION: A buffer control device 10 consists of an empty area managing circuit 14, an interruption request circuit 15, a load control circuit 13 and a buffer memory circuit 12 and the like. A direct memory access DMA writing data, an interruption data and the like from plural input and output control devices are initially stored in the circuit 12. Then, the circuit 13 follows a load permission and rejection signal from the circuits 14 and 15, feeds a load signal to the circuit 12 to carry out an indication of the load and feeds an input and output instruction executing permission and rejection signal to a CPU 20. After the circuit 13 loads the data in the circuit 12 or when the load permission and rejection signal is transmitted from the circuit 15, the circuit 13 returns a response to the respective input and output control devices to complete a bus cycle. Thereby, a sequence application of plural high speed DMA transfers, interruption requests and the like can be performed and a transfer speed between buses can be adjusted.