PURPOSE: To shorten access time and to enhance a responsiveness and a throughput of an entire of a system by setting and selecting a length of an optimum buffer memory block in accordance with a data transfer speed of I/O of an object.

CONSTITUTION: All data inputted to a buffer memory block 8 in a data buffer device 2 through an I/O data bus 4 from an I/O 1 are transmitted to a CPU 3, and the data from the I/O 1 is written in a buffer memory block 9. At this time, the device 2 newly sets an output data of an initial address register 13 in buffer address counters 10, 11. The data from the I/O 1 is written in the memory 8 and the data in the memory 9 is transmitted to the CPU 3. A similar operation thereafter is repeated until all the receiving data from the I/O 1 is completed to be transmitted to the CPU 3. Thereby, an access time can be shortened and a responsiveness and a throughput of a system can be enhanced.