Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
DATA TRANSFER CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS61210463
Kind Code:
A
Abstract:

PURPOSE: To shorten transfer preparing time and bus occupying time by providing a bus control circuit having a response section instantaneously responding a pseudo-bus permission signal and a ready signal with respect to a bus request signal of a transfer control circuit.

CONSTITUTION: When a bus line request device 1 feeds a transfer request signal A to a transfer control circuit 2, the circuit 2 feeds a bus request signal B to a bus control circuit 8. The circuit 8 receives the signal B in a response section 8-1. The response section 8-1 feeds the signal B to a bus managing section 4 through a system bus 3 and responds a pseudo-bus permission signal and a ready signal E to the circuit 2. The circuit 2 receives the pseudo-bus permission signal and transmits it to a processing section. The processing section starts a transfer preparation by the pseudo-bus signal and extends a bus transfer cycle by the inputted signal E. The managing section 4 determines an allocation of the bus, feeds a bus permission signal C to the circuit 8. The circuit 8 outputs a bus permission acknowledgement signal D to release the signal E. Thereby, a transfer preparation time is shortened and a bus occupying time can be shortened.


Inventors:
SHIRATO MASATO
HIROTA YASUO
KOJIMA KAZUNORI
Application Number:
JP5178685A
Publication Date:
September 18, 1986
Filing Date:
March 14, 1985
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
G06F13/36; G06F13/362; (IPC1-7): G06F13/26
Attorney, Agent or Firm:
Koshiro Matsuoka