BURST CLOCK CORRESPONDING MEMORY CIRCUIT

Japanese Patent JP3097737

B2

PROBLEM TO BE SOLVED: To provide a burst clock corresponding memory circuit using a burst clock signal in which correspondence to an arbitrary transmitting speed and the quality security of a stable transmission signal can be attained in transmission between the communication equipments of an opposite station and its own station.
SOLUTION: In this communication system, the constitutions of an opposite station and its own station as communication equipments are made the same, and this system is provided with a burst clock corresponding memory circuit using a burst clock signal as a clock signal for writing in a memory to be used for transmission between the communication equipments. In the burst clock corresponding memory circuit, a clock generating circuit 4 generates a reading clock signal at a transmitting speed obtained by averaging the burst clock signal which is synchronizing with it in response to a reading permission signal from a first memory 3, and a second memory 5 uses the reading clock signal as a clock signal for writing, and successively writes a transmission signal S read from the first memory 3.

Yukio Sonoda

JP1252997A

October 10, 2000

January 27, 1997

Click for automatic bibliography generation  

NEC

G06F12/00; G06F5/06; G06F13/00; G06F13/42; G11C7/00; G11C7/22; H04L7/00; (IPC1-7): H04L7/00

JP1175324A
JP4322532A
JP63116535A
JP4345231A

Yosuke Goto (1 person outside)

Previous Patent: ワンウェイクラッチ一体型ベアリング

Next Patent: LASER DIODE PACKAGE HAVING LIGHT OUTPUT MONITORING FUNCTION