PURPOSE: To eliminate the need for a data switch on each cell and to miniaturize a bus line connecting circuit with an integrated line selector LS with which this data switch is replaced by switching and connecting a sub bus line and a bus line in the order of largest bit unit data.

CONSTITUTION: Sub bus lines S1-S4 are provided. For the bit unit data which are not the largest bit unit existing in some of bus lines B1-B4, the bus lines B1-B4 and sub bus lines S1-S4 are cyclically connected and changed by the line selector LS according to the order of connection by temporary connecting circuits T1-Tn between cells C1-Cn and the sub bus lines S1-S4 at the time of the largest bit unit data. Accordingly, a lot of the data switches required for the respective cells C1-Cn can be replaced with the integrated line selector SL. Thus, the circuit can be miniaturized and the cost can be reduced.