Title:
キャッシュメモリ装置およびメモリ割付方法
Document Type and Number:
Japanese Patent JP3989312
Kind Code:
B2
Abstract:
A cache memory device comprises a secondary tag RAM that partially constitutes a secondary cache memory and employs a set associative scheme having a plurality of ways, and a secondary cache access controller that, when the number of ways in the secondary tag RAM is changed, allocates tags to respective entries so that the total number of entries constituting the secondary tag RAM and the total number of entries after the number of ways is changed are constant.
Inventors:
Kumiko Endo
Masaki Ukai
Masaki Ukai
Application Number:
JP2002197953A
Publication Date:
October 10, 2007
Filing Date:
July 05, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/08; G06F11/10; G06F12/00; G06F12/16
Domestic Patent References:
| JP1233537A | ||||
| JP50068748A | ||||
| JP5241962A | ||||
| JP51032241A | ||||
| JP10269143A | ||||
| JP62073351A |
Attorney, Agent or Firm:
Hiroaki Sakai