PURPOSE: To shorten the time required for evaluating and testing the capability of a semiconductor device.

CONSTITUTION: A local processor 14 for controlling power supply voltage, local processor 24 for controlling logical voltage, and local processor 18 for controlling timing respectively change their outputs in response to a capability test starting signal from a host processor 30 based of a basic value set by the processor 30 and coincidence-discriminated results EQ from a digital comparator 28. Then the processors 14, 24, and 18 respectively control the output voltage of a power source 13, voltages VH and VL having logical values '1' and '0' outputted from a driver 22 and discriminating reference voltages VTH and VTL having logical values '1' and '0' for binarization from an analog comparator 26, and the clock outputting timing from a timing generator 17 in accordance with programs so as to test the capability of a device 10 to be measured.