Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE TEST SYSTEM AND EVALUATION BOARD THEREFOR
Document Type and Number:
Japanese Patent JPH06180350
Kind Code:
A
Abstract:

PURPOSE: To provide a semiconductor device test system, and an evaluation board therefor, in which delay time can be measured accurately for a semiconductor device and pass/fail can be decided accurately.

CONSTITUTION: A test system 21 comprises a data memory section 28 for storing delay time differences measured by a time measuring unit 27 for driver circuits 24a, 24b, 24c,... and output terminals 22a, 22b, 22c,..., whereas an evaluation board 29 comprises a data memory section 33 for storing delay time differences between connecting terminals 31a, 31b, 31c,... and a common connecting terminal 31co. Delay time differences between respective connecting terminals can be eliminated for the evaluation board by performing correction based on the data stored at the data memory section 33 whereas delay time differences at the output terminals between respective paths can be nullified for the test system by performing correction based on the data stored at the data memory section 28 thus allowing accurate evaluation of test system and pass/fail decision of semiconductor device.


Inventors:
TSUKAGOSHI HISAO
Application Number:
JP33334892A
Publication Date:
June 28, 1994
Filing Date:
December 15, 1992
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOSHIBA CORP
International Classes:
G01R31/28; G01R31/26; (IPC1-7): G01R31/28; G01R31/26
Attorney, Agent or Firm:
Norio Ogo