Title:
CAPACITOR ARRAY TYPE D/A CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JP2964798
Kind Code:
B2
Abstract:
PURPOSE: To provide a capacitor array type D/A conversion circuit which can acquire the analog output of 100% duty without using a sampling/holding circuit that is conventionally required.
CONSTITUTION: A switch control circuit 30 controls the switches S1-S4 connected to the capacitors C1-C3 in response to a digital input signal 10. Thus the circuit 30 accumulates the charge value corresponding to the signal 10 in capacitor C4, C5. Meanwhile the circuit 30 controls the switches S5-S8 in the prescribed timing and connects the capacitors C4 and C5 to each other between an inverted input terminal and an output terminal of an operational amplifier 50. At the same time, the circuit 30 resets other capacitors (accumulated charge value is set at 0 Coulomb). Therefore the designing of a sampling/holding circuit is not required so that the layout area and the power consumption can be reduced.
Inventors:
SASAKI YASUSHI
Application Number:
JP26724492A
Publication Date:
October 18, 1999
Filing Date:
October 06, 1992
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03M1/74; H03M1/66; (IPC1-7): H03M1/74; H03M1/66
Domestic Patent References:
| JP62125714A | ||||
| JP59149723U |
Attorney, Agent or Firm:
Masanori Fujimaki