Title:
CAPACITOR MOUNTING METHOD, AND PRINTED CIRCUIT BOARD
Document Type and Number:
Japanese Patent JP2008251792
Kind Code:
A
Abstract:
To provide a capacitor mounting method which can attain a resistance and an inductance lower than those in the prior art and can sufficiently exhibit the performance of a capacitor even when a capacitor having terminals spaced by a distance shorter than a minimum via distance mountable on a printed circuit board is mounted, and to provide such a printed circuit board.
In the method of mounting a capacitor having terminals spaced by a distance shorter than a minimum via interval of the printed circuit board, sites of the printed circuit board at the terminals are cut to expose a power line or a grounding line to the air, and the terminals of the capacitor is directly soldered to the exposed power or grounding line.
Inventors:
OTSUKA EIGO
Application Number:
JP2007090635A
Publication Date:
October 16, 2008
Filing Date:
March 30, 2007
Export Citation:
Assignee:
NEC CORP
International Classes:
H05K3/34; H05K1/02; H05K1/18
Domestic Patent References:
JP2006135064A | 2006-05-25 | |||
JP2005101021A | 2005-04-14 | |||
JPH0238766A | 1990-02-08 | |||
JP2005011837A | 2005-01-13 |
Attorney, Agent or Firm:
Yasuo Ishikawa
Takahiro Imai
Takahiro Imai