To provide a simulation method for conducting simulations while adequately approximating an output load, a related program, and a simulation device.

The simulation device has a model generation function 111 for dividing a logic circuit into a plurality of partial circuits; a selective function 112 for selecting from the plurality of partial circuits a circuit of interest and a load circuit connected to the post stage, in such a manner that each of the partial circuits becomes a circuit of interest at least once; a simplification function 113 for simplifying the load circuit by specifying a transistor driven via the output terminal of the circuit of interest, and connecting to the drain of the transistor a source of virtual control voltages that varies the output potential of the transistor according to the gate potential of the transistor; and a simulation function 114 for combining the circuit of interest with the simplified load circuit to conduct simulations to evaluate the delay characteristic of each of the selected circuits of interest.