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Patent Searching and Data


Title:
CLOCK SELECTION CONTROLLING DEVICE FOR NETWORK TERMINATING DEVICE
Document Type and Number:
Japanese Patent JPS61219239
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability of the selection of the clock selection controlling device of a network terminating device, by discriminating the connecting form between the network terminating device and terminal device and selecting an appropriate retiming clock in accordance with the discriminated form and, if any possibility of mis-discrimination is considered, holding the last discriminated result.

CONSTITUTION: A received frame timing signal (c) and the output signal (b) of a monostable multivibrator 22 are compared with each other at an AND circuit 23 and the compared result is outputted as the detecting signal of 'H' or 'L' level corresponding to a connected form by means of a RS flip-flop 24 and D flip-flop 25. Moreover, when the detecting signal (d) of the case where the balanced bit just before the received frame bit is 'H' is outputted, a D flip-flop 27 holds the content of then discriminated detecting signal (h) by means of the detecting signal (d) and gives an output signal (f) corresponding to the content to the data input terminal of the D flip-flop 25 as a signal (g) through an OR circuit 28. Therefore, when the detecting signal (d) is outputted, no distance discrimination is executed and the D flip-flop 25 holds the last outputting condition and, as a result, a stable output is obtained.


Inventors:
AMAMIYA SHIGEO
KUWABARA HIDEO
MURANO KAZUO
Application Number:
JP5940285A
Publication Date:
September 29, 1986
Filing Date:
March 26, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L7/00; H04L7/033; (IPC1-7): H04L7/00; H04L7/02; H04L11/02
Attorney, Agent or Firm:
Aoki Akira