To simplify a system LSI design satisfying complicated timing constraints and shorten the design period by facilitating and streamlining the system LSI design.

In a clock tree generation apparatus 200, an acquisition part 201 acquires a net list of a clock tree 300, synchronous group information, and placement information about circuit elements such as FFs to determine whether or not a synchronous group A or B includes a pin interposed in a clock path. If there is no such a pin, conventional clock synthesis is performed. When a specification part 202 specifies an input pin 304 of a clock gate 303 because the input pin 304 of the clock gate 303 is a pin interposed in a clock path, the clock tree 300 is divided. Specifically, a first sub-tree 321 having the clock gate 303 with the specified input pin 304 as a sub-route and having a circuit element group 311 coupled direct to the clock gate 303 as a terminal is divided from the clock tree 300.