To provide a color difference clamp constitution which avoids erroneous introduction of offsets in, particularly, a system having a cascade clamp by accurately setting a blanking interval at the center of the extent of an analog/digital converter.

A color video display signal processor includes sources (U2-U13 and U15) of color difference signals (Pr and Pb) and the analog/digital converter (U3) which converts the color difference signals (Pr and Pb) into digital signals (D). In order to generate clamp voltages (Vpr and Vpb), a potential divider (401) is coupled with the reference voltages (Vrt and Vrb) of the converter (U3). Clamp constitutions (U43 and U44) are coupled with the color difference signals (Pr and Pd) and converter (U3) and receive reference clamp voltages. The clamp constitutions (U43 and U44) couple the clamp voltages with the color difference signals (Pr and Pb) in response to a clamp pulse (Hs).