PURPOSE: To prevent the disorder of respective pulse intervals of a reference signal and a signal to be synchronized, by generating a trigger signal by counting down one of two reference signals, and correcting a shift to the reference signal by resetting the signal to be synchronized, when said trigger signal is generated.

CONSTITUTION: A synchronization timing generating circuit 31 counts down a reference signal A and generates a synchronization timing signal C. In a frequency dividing circuit 32, a trigger signal Pt is generated by synchronizing with a pulse P1 of the nearest reference signal B from the time point of a rise of this synchronization timing signal C, and a recording signal use clock D before that time is reset. Subsequently, from the next pulse p2 of the pulse p1, the recording signal use clock D which has frequency-divided the reference signal B is generated again. In such a way, even if a phase difference exists between the pulse p2 and the reference signal A, its difference is below a period of the pulse p1 and p2, and if the frequency of the reference signal B is high, it does not become a problem. In the same way, at every generation (rise) of the synchronizing timing signal C, the trigger signal Pt is generated, the recording signal use clock D is reset and the out of synchronism is corrected.