PURPOSE: To prevent the destruction of a content in RAM by approving access to RAM only when CPU executes the processing of a prescribed program stored in ROM.
CONSTITUTION: ROM 3, ROM 4 and an I/O interface 6 are connected to CPU 1 through a data bus and an address bus. A chip selector 2 is connected to CPU 1, and the selection signal of the chip selector 2 is directly inputted to ROM 3 and to RAM 4 through an OR gate 5. ROM 3 and ROM 4 can be accessed only when a port connected to the chip selector 2 becomes 'Low' and it can access to RAM 4 only when CPU 1 executes the processing of the program stored in ROM 3. Consequently, CPU cannot access to RAM 4 in a state where ROM 3 is not connected to CPU 1. Thus, the destruction of the backup data stored in RAM is prevented.
OGIDA KAZUYUKI
OKAMOTO YUJI
