Title:
DATA COMMUNICATION SYSTEM INCORPORATING MULTICORE COMMUNICATION MODULE, AND ITS METHOD
Document Type and Number:
Japanese Patent JP2004178570
Kind Code:
A
Abstract:
To provide a multicore SOC enabling communication among processors having different data and/or address formats, or using different communication mechanisms.
An address of a memory space for FIFO or the like is related to an address of a data processor by using an address table (148). Counters (150 and 152) each coupled to the FIFO supplies a flag or a ready signal indicating the not-full or not-empty status of the respective FIFO which is supplied to a master device (104) that is writing data to the FIFO or that is reading data from the FIFO so that the writing master device will write only when the FIFO is not full, and the reading master device will read the data only when the FIFO is not empty.
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Inventors:
EMERSON STEVEN M
HAMMITT GREGORY
KOPACEK STEVEN
HAMMITT GREGORY
KOPACEK STEVEN
Application Number:
JP2003375486A
Publication Date:
June 24, 2004
Filing Date:
November 05, 2003
Export Citation:
Assignee:
LSI LOGIC CORP
International Classes:
G06F13/10; G06F13/00; G06F13/16; G06F13/40; G06F15/80; H04L12/46; (IPC1-7): G06F13/10; H04L12/46
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko