Title:
DATA DELIVERY SYSTEM OF MULTI COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPS5448461
Kind Code:
A
Abstract:
PURPOSE:To improve the memory efficiency of the processing side by make transmission with the station address of the processor added from the processing request interruption from the input and output unit,using this added address, and by managing the processor having interrupt. CONSTITUTION:The communication between two sets of processors 2A and 2B is made by using the global memory 1 and the linkage unit 5. To auxiliary memories 7A and 7B, the operation system corresponding to each processor, application program, and various files are stored, and the multiplex input and output control units 6A and 6B are connected so that if the main processor 2A or 2B is down, other processors 2B or 2A is recovered. The master station 8 is connected to the unit 2 side to the data highway loop 10, and the input and output control unit consisting of the display units 11A and 11B is connected to the remote station 9.
Inventors:
ODAKA YUKIO
HAYASHI TOSHIHIRO
HAYASHI TOSHIHIRO
Application Number:
JP11460177A
Publication Date:
April 17, 1979
Filing Date:
September 26, 1977
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F15/16; G06F3/00; G06F15/177; (IPC1-7): G06F3/00; G06F15/16
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