Title:
DATA DISTRIBUTION SYSTEM FOR MULTIPROCESSOR
Document Type and Number:
Japanese Patent JPS63276161
Kind Code:
A
Abstract:
PURPOSE:To grasp a slave processor kept in a ready state with simple control by providing a stack which checks anyone of plural processors that is kept in a ready state. CONSTITUTION:A master processor 1 contains registers AO and DO and is connected with a memory 2 and DM1-5 of a data area memory 3 provided in response to plural slave processors PS1-5 respectively. A control stack MS of the memory 2 stores the head addresses of the DM1-5 of the memory 3 and an EOB. The head address of the stack MS is written at first in a pointer PT. When the processor 1 delivers data to a slave processor, the pointer PT is read into the register AO and a ready state of the slave processor is decided when the contents addresses by the PT are not equal to the EOB. Then data is delivered and at the same time 1 is added to the PT. When processors SP1-5 end the prescribed jobs, the processor 1 subtracts 1 from the PT.
Inventors:
ISHIZAKI HIROMI
Application Number:
JP11096387A
Publication Date:
November 14, 1988
Filing Date:
May 07, 1987
Export Citation:
Assignee:
RICOH KK
International Classes:
G06F15/16; G06F15/17; G06F15/177; (IPC1-7): G06F15/16
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