PURPOSE: To execute other processes by a CPU during a DMA without providing a sub CPU and a shared memory by separating the CPU from an internal bus by a bus control means while executing the DMA.

CONSTITUTION: When a DMA control part 2 controls a data transfer, a bus mediation part 5 controls a bus control part 6. And while making the output sides of a buffer part 6-1 and a latch part 6-2 a high impedance and separating a CPU 1 from an internal address bus 7 and an internal data bus 8, the data transfer between an I/O control part 4 and a memory 3 is executed. Therefore, the CPU 1 can access another I/O control part and memory 10. And even during the DMA, the CPU 1 can execute only the first right operation by latching an address and data in the latch part 6-2. Thus, without using the sub CPU and the shared memory, it is possible to separate a bus executing a DMA transfer from the CPU 1, so the CPU 1 can execute other processes.