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Patent Searching and Data


Title:
DC OFFSET COMPENSATION METHOD AND ELECTRONIC CIRCUIT USING THE SAME
Document Type and Number:
Japanese Patent JP2004159140
Kind Code:
A
Abstract:

To reduce influences of noise upon a comparator when obtaining compensation data to be used by a D/A converter for compensating a DC offset voltage of an analog output signal by successive comparison operation of the comparator.

This electronic circuit is equipped with a D/A converting circuit 2, a comparator 3 for comparing voltage of the analog signal outputted from the D/A converting circuit with a DC offset voltage in an output signal of a circuit 1 to be corrected, an offset compensation register 4 for obtaining each bit of the compensation data to be inputted to the D/A converting circuit so as to compensate the DC offset voltage by the successive comparison on the basis of the comparison result of the comparator 3, and a register 5 for majority decision for storing N pieces of values regarding each of specified bits in order to perform majority decision on the basis of the N pieces of values obtained by comparison for N times (N is an odd number equal to or larger than 3).


Inventors:
KOBAYASHI NORIKO
Application Number:
JP2002323538A
Publication Date:
June 03, 2004
Filing Date:
November 07, 2002
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H03M1/10; H03F3/34; (IPC1-7): H03M1/10; H03F3/34
Attorney, Agent or Firm:
Mutsumi Yanase
Nao Iku Suzuki
Masaaki Utsunomiya
Atsushi Watanabe