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Title:
DC OFFSET ELIMINATION CIRCUIT
Document Type and Number:
Japanese Patent JP2002176458
Kind Code:
A
Abstract:

To provide a DC offset elimination circuit that can eliminate a DC offset that is a problem of a CIC(Cascade Integrator-Comb) filter with a simple configuration adopting only adders without the use of multipliers causing the configuration to be complicated.

The DC offset elimination circuit that eliminates a DC offset of an input signal is provided with a polarity discrimination device 211 that discriminates a polarity of an output signal from the DC offset elimination circuit, an adder 215 and an offset register 216 that apply accumulation processing to outputs of the polarity discrimination device 211, a K-bit shifter 217 that shifts downward the accumulation processing result by an optional number of bits, and an adder 210 that sums an output of the K-bit shifter 217 and the input signal and provides an output of the sum as an output signal externally.


Inventors:
NAITO MASASHI
Application Number:
JP2000372539A
Publication Date:
June 21, 2002
Filing Date:
December 07, 2000
Export Citation:
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Assignee:
HITACHI INT ELECTRIC INC
International Classes:
H04L27/22; H04L27/38; (IPC1-7): H04L27/22; H04L27/38
Attorney, Agent or Firm:
Hisako Ishido (3 outside)