Title:
DECODING CIRCUIT FOR VARIABLE LENGTH CODE
Document Type and Number:
Japanese Patent JP3008685
Kind Code:
B2
Abstract:
PURPOSE: To decode a bit variable length code at high speed by deciding a shift amount at the low-order part of data read from a variable length decoding table in the case of decoding end by using a shift control circuit.
CONSTITUTION: Assuming that an initial address set to a start address register 101 is described in the same format as that of a variable length decoding table 103a, the initial address is passed through a multiplexer 105 later, and the least significant four bits are replaced with the leading four bits of a shift register 107 storing data to be decoded. Before that replacement, a multiplexer 111 for sub block address is used for designating the range of the replacement, and an inverter 108a is used. Namely, when the least significant field two bits of an output from the multiplexer 105 are '01', the replacement of the least significant two bits is generated. Namely, the central field two bits of the output from the multiplexer 105 are turned to the output of the multiplexer by ignoring the leading two bits of the inverter 108a.
Inventors:
Yasushi Oi
Application Number:
JP20634592A
Publication Date:
February 14, 2000
Filing Date:
August 03, 1992
Export Citation:
Assignee:
NEC
International Classes:
G06F5/00; H03M7/42; (IPC1-7): H03M7/42
Domestic Patent References:
| JP62135015A | ||||
| JP62146022A | ||||
| JP63301626A | ||||
| JP2266615A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)