PURPOSE: To enable to obtain arbitrary delay time, by altering the period of address signal, in the delay circuit using RAM as the delay element.

CONSTITUTION: The output data D3 delayed by N1 sets of clock pulses CP can be obtained through the shift circuit 3 for the input data DO. Next, the data D3 is written in the RAM 4 with the address signal D5 of the address counter 5 taking the time of N2 sets of pulse CP number as the period. Further, the RAM control circuit 6 controlling the write-in operation after readout reads out the data of the address designating the address signal temporarily stores it in the latch circuit 7. Accordingly, the data D3 written in RAM 4 is delayed for the time corresponding to the period of the signal D5 of the counter 5 for the data D4 read out with the next address designation. The data D4 is the data D1 delayed by one clock with the circuit 7. Thus, arbitrary dealy time can be obtained with the setting of the period of the address signal