To provide a design method for a synchronizing circuit by which the circuit can be divided entirely at random and an EMI noise caused by a peak current is prevented from increasing because of an increased peak current at clock leading or training with an increase in the circuit scale with respect to the design of the LSI synchronizing circuit.

In the design method for the synchronizing circuit, the circuit provided with flip-flops and combination circuits is divided into blocks, each block configures a clock tree, and a clock of each block receive a signal delayed by a buffer and the increase in the peak current is relaxed even when the circuit scale increases to thereby realize a reduction in the EMI noise independently of the presence / absence of exchange between the blocks.