Title:
DIFFERENTIAL BUFFER WITH IN-PHASE MODE REMOVING FUNCTION
Document Type and Number:
Japanese Patent JP3808306
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a differential buffer, which has high in-phase mode removing performance.
SOLUTION: A clock circuit on an integrated circuit chip has a differential buffer, equipped with an in-phase mode removing circuit. The differential buffer is equipped with 1st and 2nd DC paths, each of which is equipped with FETs (31 to 38) connected to form a cascade circuit. A tap 58 of the 1st path supplies a bias voltage to gate electrodes of FETs of the 1st and 2nd paths. The gate electrodes of the FETs of cascade circuits of the 1st and 2nd paths are so coupled, that they are biased with relative source voltages of the buffer.
Inventors:
Johnny Kew Tsang
Application Number:
JP2000372564A
Publication Date:
August 09, 2006
Filing Date:
December 07, 2000
Export Citation:
Assignee:
HEWLETT-PACKARD COMPANY
International Classes:
G06F1/10; H03K5/08; G06G7/14; H03F1/30; H03F3/30; H03F3/34; H03F3/45; H03K5/02; (IPC1-7): H03K5/08; H03F1/30; H03F3/34; H03F3/45; H03K5/02; //G06F1/10
Domestic Patent References:
| JP3077413A | ||||
| JP59148416A | ||||
| JP62120109A | ||||
| JP63132509A |
Attorney, Agent or Firm:
Kaoru Furuya
Takahiko Mizobe
Satoshi Furuya
Takahiko Mizobe
Satoshi Furuya
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