To provide a technology for achieving multiplication suitable for a product-sum operation using an analog circuit.
A differential multiplication circuit 4 is provided with a transistor pair 1 equipped with two first transistors whose source terminals are connected to each other, wherein the differential voltage value of voltages to be applied to the gate terminals of the two first transistors correspond to a value to be multiplied; a second transistor 2 connected to the source terminal of the transistor pair 1, with a gate terminal applied with a voltage corresponding to a multiplication value; and a current mirror circuit 3 connected to the drain terminals of the transistor pair 1. Then, currents corresponding to the result of multiplying the multiplication value and the value to be multiplied are outputted from one drain terminal of the transistor pair 1.
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MORIE TAKASHI
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura