PURPOSE: To generate an output time reference signal representing correctly a delay by selecting correctly an integer N (N=1, 2,∼) to an expected delay range even when the delay exceeds the period of an input time reference signal.

CONSTITUTION: An output of NAND gates 16, 17 is inputted respectively to an LOAD terminal (LD) of counters 18, 19, where the delay amount depends on the timing set to each counter. The counters 18, 19, when a delay 2T-D is set, a clock number corresponding to a D is elapsed and the count reaches 2T, generates a carry signal C0(CARRY), and OR of the C0 outputs of the counters 18, 19 is the output time reference signal 13. The delay of the counters 18, 19 is set alternately by the LOAD pulse at each period T and the OR of the C0 outputs generated alternately is outputted, then the output time reference signal corresponding one to one to the input time reference signal 11 is obtained with the delay in a range from 0 to 2T.