PURPOSE: To connect a direct memory access (DMA) controller element whose address width is different by providing an address generating means and supporting the address space of a microprocessor together with an address bit from the DMA controller element.

CONSTITUTION: An address generating means 6 is provided to generate address bits A31-A24 supported by a microprocessor 1 but not supported by a DMA controller element 2 in a hardware. When signals A23-A00 showing DMA transfer are received, this address generating means 6 goes to an enable state and the address space of the microprocessor 1 is supported together with the address bit from the DMA controller element 2. Thus, the microprocessor 1 and DMA controller element 2 whose address widths are different, can be connected.