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Title:
DISPLAY DATA CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH01227189
Kind Code:
A
Abstract:

PURPOSE: To shorten the operation time of the title circuit from the data reception starting time to the data display starting time by fetching transmitted signals at high speed by processing the data to be fetched during a non-display period in the form of codes, as it is.

CONSTITUTION: In a teletext system, a microprocessor (CPU) 11 decodes transmitted data and discriminates whether the transmitted data are of the pattern form or code form or colored data. When the data are of the code form, the code data are stored in a character code memory 22 as they are through a bus 12 and gate circuit 21. Therefore, it is not required for code-form data especially to write the data in a pattern memory section after converting the data into pattern data at a character memory. Therefore, the display processing time of this circuit can be shortened.


Inventors:
MATSUSHITA AKIRA
Application Number:
JP5252688A
Publication Date:
September 11, 1989
Filing Date:
March 08, 1988
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G09G5/40; G09G1/00; G09G1/02; G09G5/00; G09G5/02; H04N7/025; H04N7/03; H04N7/035; H04N7/08; (IPC1-7): G09G1/00; G09G1/02; H04N7/08
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)