Title:
表示装置、表示モジュール及び電子機器
Document Type and Number:
Japanese Patent JP5801447
Kind Code:
B2
Abstract:
A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.
Inventors:
Shunpei Yamazaki
Kengo Akimoto
Shigeki Komori
Hideki Uochi
Nimura Tomoya
Kasahara Takahiro
Kengo Akimoto
Shigeki Komori
Hideki Uochi
Nimura Tomoya
Kasahara Takahiro
Application Number:
JP2014108807A
Publication Date:
October 28, 2015
Filing Date:
May 27, 2014
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G09F9/30; G02F1/1368; H01L21/28; H01L21/822; H01L27/04; H01L29/786; H01L51/50; H05B33/14
Domestic Patent References:
| JP11183876A | ||||
| JP11288007A | ||||
| JP2008089915A | ||||
| JP2007065615A | ||||
| JP2008176089A | ||||
| JP2008152084A |