To provide a dot clock circuit generating automatically a dot clock having a frequency being coincident with a dot period.

Dot clocks CLK outputted from a PLL means 2 are counted and calculated by a calculating means 5 in a period in which a detecting signal 3X is made first a high level from a rising edge of a horizontal synchronizing signal H, and in a period in which the signal is made last a high level, difference between a display period and the result of calculation is repeatedly calculated after finish of calculation of one vertical scanning period, and the maximum value of a display period is obtained. After that, when a control means outputs a frequency division ratio to the PLL means 2, a programmable frequency divider 22 frequency-divides the dot clock CLK, horizontal resolution outputted by a discriminating means 4 is compared with a display period outputted by the calculating means 5, it is performed until horizontal resolution is equalized to a display period.