PI/4 DQPSK MODULATOR PROVIDED WITH COARSE MAPPER PRE-SESSION AND FINE FILTER PRE-SESSION

Japanese Patent JP3659711

B2

PROBLEM TO BE SOLVED: To reduce the memory capacity required for a π/4 DQPSK filter on a ROM base by configuring the modulator with a mapper that generates a modulation state symbol, a shift register that provides an output of a sequence of a symbol, and a ROM and an IQ modulator that generate I and Q control variables.
SOLUTION: A serial digital data stream 1 is given to a shift register 2 of an IQ modulator, where bit pairs are generated through S/P conversion. A clock signal 3 is given to a frequency divider 4, which generates a signal NEW-SYM 5 every time a new bit pair is received by the register 2. The signal SYM 5 is given to a frequency divider 6, which outputs a signal EVEN-ODD 7. The signal 7 is given to a switch MUX 8 and a program data symbol is fed to a mapper 9 or 10 from the register 2 when the program data symbol is an even number or odd number and the symbol is converted into a modulation state symbol. The output is given to a MUX 11, from which CK and DK outputs are given respectively to shift registers 14, 15. On the other hand, the signal 5 is given to a control input of the registers 14, 15. Signals LAST-C16 and LAST-D17 are outputted from the registers 14, 15. Signals 16, 17 are given to the mappers 9, 10 as their inputs.

Brian pee fetts

JP26508395A

June 15, 2005

October 13, 1995

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AGILENT TECHNOLOGIES, INC.

H04L27/20; (IPC1-7): H04L27/20

JP6112981A
JP621765A
JP6252961A
JP522355A

Kaoru Furuya
Takahiko Mizobe
Satoshi Furuya

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